The present invention relates to a technique to generate a checking environment for a new circuit developed while maintaining the equivalence of a flow (functions or behaviors of the circuit), and for example, relates to a technique which is effective when applied for the generation of a test environment of a semiconductor integrated circuit extended in function while maintaining the flow equivalence, and the test using the test environment.
Patent document 1 (Japanese patent laid-open No. 2005-316595) describes an invention which relates to a technique to judge, in a simulation, the equivalence between a circuit description of operation level described in a system level design language and an RTL (Register Transfer Level) circuit description described in an HDL (Hardware Description Language). In this technique, equivalence judgment is carried out by carrying out simulations individually for the respective circuit descriptions and judging whether the order of waveforms in signal value transition is maintained after acquiring information about signal waveforms. Consequently, individual test benches (programs for generating a test pattern to test a circuit description) are configured for the respective circuit descriptions, and therefore, it is not possible to realize equivalence judgment using an identical test bench.
Patent document 2 (Japanese patent laid-open No. 2003-141202) describes an invention, which has been developed for the purpose of checking whether the modification/operation is carried out correctly in each internal process by focusing attention on the internal process stage in operation composition, wherein equivalence judgment before and after the composition is carried out. In this technique, whether the modification of description is carried out correctly in each deformation process of an input description carried out by an operation composition tool is proved by directly accessing an intermediate representation generated by the operation composition tool in each deformation process. An equivalence checking is carried out by extracting respective EFSMs (Extended Finite State Machines) from the intermediate representations before and after the deformation process, finding next state functions and output functions of the respective EFSMs in a symbolic simulation, and checking whether the obtained next state functions and output functions are equal to each other. That is, the technique described in patent document 2 is not an equivalence checking technique by a simulation using a test bench.
Patent document 3 (Japanese patent laid-open No. 2004-145712) describes an invention, which has been developed for the purpose of making it possible to carry out equivalence checking by comparing an input description to operation composition and resultant waveforms of a simulation of an output result RTL, wherein the equivalence judgment before and after the composition is carried out. In this invention, the equivalence checking of the input description and the output description is carried out by simulating the input description to the operation composition and the output result RTL individually, identifying the correspondence of transaction in each output waveform using information of cycle specification assigned to the input description or cycle information inserted by the operation composition, and comparing the output waveforms in units of transactions. Consequently, a description of a test bench is required for each of the input description and the output result RTL.